High-density inter-die interconnect structure

ABSTRACT

An interconnect architecture for connecting a plurality of closely-spaced electrical elements on a first integrated circuit fabricated structure with operative circuits on a second integrated circuit fabricated structure. In one embodiment, the first integrated circuit fabricated structure comprises a plurality of photo sensors. Conductive interconnect elements on the first integrated circuit fabricated structure provide electrical connection between individual photo sensors and the operative circuitry on the second integrated circuit fabricated structure.

FIELD OF THE INVENTION

[0001] The present invention is directed to an interconnect structurefor semiconductor die and, more specifically, the invention relates toan interconnect structure for die where the circuits on at least one dieare separately and independently operable and closely spaced.

BACKGROUND OF THE INVENTION

[0002] Various types of imagers or image sensors are in use today,including charge-coupled device (CCD) image sensors and complementarymetal-oxide semiconductor (CMOS) image sensors. Thesesemiconductor-based image sensors are widely used in many image inputdevices because they can be mass produced using advanced fine-patterninglithographic techniques. Applications include digital cameras, computerperipherals for document capture, visual communications, and facsimilemachines.

[0003] A CCD image sensor utilizes an array of photo sensors to formcharge packets proportional to the received light intensity. These photosensors are typically photo transistors or photo diodes located on theimage sensor surface. Each charge packet constitutes a pixel of thecomposite image. The image data is read out from the CCD array byshifting these analog charge packets from the CCD array interior to theperiphery in a pixel-by-pixel manner. To begin the readout process, thecharges on the first row are transferred to a readout register and fromthere the signals are input to an amplifier and in most applications toan analog-to-digital converter. Once a row has been read, its charges onthe readout register row are deleted. The next row then enters thereadout register and all the rows above move down one row. In this way,each row is read, one row at a time. Because all the pixels in a row ofpixels are read simultaneously, the pixels of the CCD array are notindividually addressable.

[0004] Due to voltage, capacitance and process constraints, CCD arraysare not well suited to integration at the high levels of integrationpossible in CMOS integrated circuits. Hence, any supplemental signalprocessing circuitry required for the CCD image sensors (e.g., memoryfor storing information related to the sensor) is generally provided onone or more separate chips. As a result, the system cost and size areincreased. It is also known that CCD image sensors require a large powerconsumption and higher operating voltages, as compared with conventionalCMOS signal processing circuitry.

[0005] CMOS image sensors typically utilize an array of active pixelimage sensors and a row or register of amplifiers to sample and hold theoutput of a given row of pixel image sensors. The principle of a CMOSpixel's operation is based on the modulation of a reverse biased pnjunction capacitance (of a diode, for example) due to impinging light.Photons absorbed in the depletion region of the reverse biased junctiongenerate electron-hole pairs that discharge the reverse biasedcapacitance. Larger junctions collect more photons and are moresensitive to light, but larger junctions also reduce the resolution of asensor because fewer pixels can be placed on the available surface area.

[0006] CMOS image sensors have several advantages over CCD imagesensors. CMOS image sensors are formed with the same CMOS processtechnology used for the associated circuitry required to operate theCMOS image sensor and therefore the sensors and support circuitry areeasily integratable into a single chip. Single chip integration easesminiaturization, lowers manufacturing costs, and boosts reliability.Using CMOS image sensors, it is possible to create a monolithicintegrated circuit providing not only the sensor but also control logicand timing, image processing, and signal-processing circuitry. Thus theCMOS image sensors can be manufactured at lower cost, relative to CCDimage sensors, using conventional CMOS integrated circuit fabricationprocesses. Also, the CMOS image sensors operate at a lower operatingvoltage and consume less power, allowing the system into which thesensors are incorporated to operate longer on batteries, which is amajor advantage for hand-held imaging products. Finally, each CMOS imagesensor is accessible over a grid of x-y lines, instead of using theshift register process of charged coupled devices. The column and rowaddressability of the CMOS image sensor, which is similar to theconventional RAM readout process, allows windowing of the image. CMOSimage sensors require only a single power supply to drive both the imagesensor and the associated circuitry. By contrast, CCD image sensorstypically require three different input voltages. Also, CCD imagesensors lack a consistent dark level voltage due to fabricationprocessing imperfections. CMOS image sensors are also known to exhibitinconsistent dark levels, but the associated CMOS signal processingcircuitry can track the dark level for each CMOS image sensor andprovide a compensation factor during the signal processing function sothat a uniform dark level is achievable across the CMOS image sensorarray.

[0007] However, CMOS image sensors are not without disadvantages. Theuse of state-of-the-art CMOS integrated circuit fabrication techniquesfor the associated signal processing circuitry, and the CMOS imagesensor would compromise the construction of the CMOS photo sensors,thereby reducing the image signal quality. For example, typicalsubstrate and source/drain doping levels (or retrograde doped tubs wherethe doping level at the surface is lower than the doping level below thesurface) conventionally used in CMOS processes are higher than thedoping levels that provide optimal image sensor quality. Reducing thedoping levels to achieve better sensor sensitivity, dynamic range, orcolor balance, would significantly degrade the performance of the CMOSprocessing circuitry. Therefore, higher levels of component integration(i.e., image sensors and operative signal processing circuitry on thesame chip) are therefore not practical.

[0008] Further, in those situations where the CMOS image sensor and itssignal processing circuitry are co-located on the same integratedcircuit, the associated circuits consume a portion of the availablepixel area, resulting in a larger overall chip area and reducing theimage fill factor (the ratio of the active pixel area to the total pixelarea). The efficiency, resolution and sensitivity of the CMOS imagesensor array is in turn disadvantageously reduced. Also, certain CMOSmaterial layers (e.g., salicide layers) may be partially or completelyopaque, reducing the image sensor sensitivity. In an effort to overcomethe disadvantages created when using state-of the-art CMOS processtechnology in conjunction with CMOS image sensors, certain modified CMOSprocesses have been created that remove processing steps or alter devicephysical characteristics to improve the image sensor signal quality.Although removal of these process steps improves image sensor signalquality, the CMOS technology is generally compromised. In summary, itcan be said that state-of-the-art CMOS image sensor processingtechnology lags by several generations the current state of the CMOSprocessing art.

SUMMARY OF THE INVENTION

[0009] To overcome the disadvantages discussed above relative to the useof CMOS image sensors and associated CMOS operative circuitry, thepresent invention provides an interconnect system between a firstintegrated circuit structure having a plurality of image sensorsfabricated therein and a second CMOS (or other integrated circuit type,for example, BiCMOS) integrated circuit structure having signalprocessing circuitry operative in conjunction with the image sensors.With the separation of the image sensor structure and the operativesignal processing circuitry, the image sensor structure can befabricated with processing techniques that are specifically optimizedfor the image sensors, and the signal processing circuitry can also befabricated with uniquely optimal fabrication techniques and devicecharacteristics. The interconnect system comprises electroless nickelplated bumps, solder bumps or other well-known die interconnectstructures, especially fine pitch interconnect structures. The bumps areprovided on the image sensor structure for interconnecting each imagesensor or pixel element with its associated signal processing circuitrylocated on a separate structure. Mating die interconnect structures arealso included on the signal processing circuitry for connection to eachof the pixel elements of the image sensor structure. After fabricationof the two individual structures, the image sensor structure is bondedto the signal processing structure by way of the mating die interconnectstructures. According to the teachings of the present invention, the useof separate image sensor and signal processing structures allows thefunctional characteristics and processing methodology of each structureto be optimized by use of the most favorable fabrication processingsteps and device characteristics.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present invention can be more easily understood and thefurther advantageous and uses thereof more readily apparent, whenconsidered in view of the description of the preferred embodiments andthe following figures in which:

[0011]FIG. 1 illustrates a typical CMOS image sensor array;

[0012]FIG. 2 illustrates a prior art CMOS image sensor circuit;

[0013]FIG. 3 is a time line showing the operational phases of the CMOSimage sensor circuit of FIG. 2;

[0014]FIG. 4 is a cross-sectional view of first and second integratedcircuit structures interconnected according to the teachings of thepresent invention; and

[0015]FIG. 5 illustrates doping regions for the CMOS image sensorcircuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] The processing steps and hardware components of the presentinvention have been represented by conventional processes and elementsin the drawings, showing only those specific details that are pertinentto the present invention so as not to obscure the disclosure withdetails that will be readily apparent to those skilled in the art havingthe benefit of the description herein. Exemplary device layers are notshown to scale. Like reference characters represent like structureselements throughout.

[0017] Bulk semiconductor materials can be used as photo conductors(also referred to as photo sensors or image sensors) based on the changein the semiconductor resistance as a function of the wavelength andintensity of the impinging light waves. Electrons in bound states in thevalence band (for intrinsic semiconductor material) or indoping-determined energy levels within the forbidden band gap (forextrinsic semiconductor materials) absorb energy from the incident lightphotons and are excited into free states in the conduction band. Theelectrons remain in the excited state for a characteristic lifetime. Theconduction of electrical current takes place as a result of movement ofthe electrons in the conduction band or movement of the positive holesformed in the valence band. The resistance of the semiconductor materialis thus inversely proportional to the illumination and this resistancechange is translated into a change in the current that flows through thedevice output circuit.

[0018] In lieu of simple semiconductor bulk photo sensors, photo sensorjunction devices can be used to improve the speed of response and thesensitivity of the detector to optical radiation. Such two-terminaldevices designed to respond to photon absorption are referred to asphotodiodes. In a conventional reverse-biased diode, carriers generatedwithin the depletion region drift away from the depletion region due tothe electric field; electrons are therefore collected in the n regionand holes in the p region. These carriers form the reverse current.Also, minority carriers generated thermally within a diffusion length ofthe edge of the transition region diffuse to the depletion region andare swept to the other side by the electric field. If the junction isalso uniformly illuminated by photons having an energy greater than thesemiconductor material band gap, then these electron-hole pairs alsoparticipate in the reverse current. This is the basic principle by whicha reverse-biased diode detects light. Although electron-hole pairs arealso generated outside the depletion region, they do not result incurrent flow.

[0019] Generally, a CMOS image sensor, to which the teachings of thepresent invention can be applied, is an integrated circuit that measuresincident light by detecting a voltage change produced by a photo sensor.Specifically, a photo sensor is charged to a pre-determined voltage andthen integrates the incident light, the result of which is a highervoltage across the device. The voltage value of the photo sensor is thenread out by a readout circuit, wherein this voltage value isrepresentative of the incident light.

[0020]FIG. 1 illustrates a block diagram of a conventional CMOS imagesensor array 100. Each element in the array (such as array elements 161,162 and 163) is an individual CMOS image sensor circuit, the details ofwhich will be discussed below in conjunction with FIG. 2. The individualCMOS image sensor circuits are also referred to as pixel circuits orpixel elements.

[0021] The CMOS image sensor array 100 is controlled by a row decoder110 and a column decoder 120, which are individually activated to selecta specific CMOS image sensor circuit for activation. The output of theactivated CMOS image sensor circuit is carried down a column output line164 to a sense and hold circuit 130. The sense and hold circuit 130senses the voltage value of the activated CMOS image sensor circuit.Finally, the sensed voltage value is converted to a digital value by ananalog to digital converter 140. The output signal from the analog todigital converter 140 is a digital signal representative of the lightintensity.

[0022] A CMOS image sensor array, such as the array 100, is similar to adynamic random access memory array except that instead of individualmemory cells that are set and later read out, a CMOS image sensor arrayhas individual CMOS image sensor circuits that are set to an initialvoltage value and then sensed after exposure to incident light.Furthermore a CMOS image sensor array differs from a dynamic randomaccess array in that analog values are stored within each CMOS imagesensor and then quantitized by conversion in the analog to digitalconverter 140.

[0023]FIG. 2 illustrates an exemplary CMOS image sense circuit 161,comprising a reset transistor 230, a photo sensor 220, a source followertransistor 240 and a row select transistor 250. Also illustrated in FIG.2 is an exemplary output circuit for processing the output signal of theCMOS image sense circuit 161. In particular, the output circuitcomprises a current source transistor 280 and a sensor circuit 290.

[0024] The CMOS image sense circuit 161 operates in three differentphases: reset, integration and readout. The operational phases of theCMOS image sense circuit 161 are described below with reference to FIG.3, which displays the gate voltage of the source follower transistor 240during operation of the CMOS image sense circuit 161.

[0025] Initially, during a reset phase 310 (see FIG. 3) the photo sensor220 is charged, i.e., reverse biased, by the voltage source V_(DD), to areset voltage level via the reset transistor 230. The actual voltage atthe cathode terminal of the photo sensor 220 is V_(DD)−V_(TN), whereV_(TN) is the voltage drop across the reset transistor 230. This chargevoltage level is referred to as the “reference black” voltage level(V_(RB)).

[0026] Next, during an integration phase 330 (FIG. 3) the photo sensor220 is exposed to incident light that is to be measured. As discussedabove, photons striking the depletion region of the photo sensor 220,cause an increase in the reverse current flowing to the gate terminal ofthe source follower 240. The voltage of the remaining charge on thephoto sensor 220 is proportional to the number of photons that strikethe photo sensor 220. Thus, during the integration phase 330, thevoltage on the gate of the source follower 240 drops. A white referencelevel is reached as the cathode terminal of the photo sensor 220approaches the negative power supply voltage, in this case ground. Ablack level occurs when no photons are integrated, such that the photosensor voltage essentially remains at the original reference blackvoltage level of V_(RB)=V_(DD)−V_(TN).

[0027] Finally, during a readout phase 350 (see FIG. 3) the row selecttransistor 250 is activated such that the gate voltage of the sourcefollower transistor 240 is measured by the sensor circuit 290. In oneembodiment, measurement of the photo sensor voltage is performed using acorrelated double sampling circuit. First, the integrated photo sensorvoltage signal is sampled. Then the CMOS image sensor circuit 161 isreset and the reset voltage is sampled to obtain the reference blackvalue. The desired signal representing the incident light is thedifference between the integrated photo sensor voltage and the photosensor reset voltage.

[0028] According to the teachings of the present invention, it isadvantageous to separate the photo sensor 220 from the related circuitrysuch as the transistors illustrated in FIG. 2 and the sensor circuit290. In this way, the fabrication processes required to optimize thecharacteristics of the photo sensor 220 can be employed during thefabrication of the photo sensor array. Similarly, the fabricationprocesses required to optimize the functionality of the relatedcircuitry can be employed as the circuitry is fabricated. The twostructures are then interconnected as taught by the present invention.

[0029] Flip chip interconnect technology employs the use of bead-liketerminals formed on one surface of a chip or monolithic semiconductordevice to bond the flip chip to another electronic device, such as acircuit board. The bead-like terminals, also referred to as bumps, serveboth to mechanically secure the flip chip to the circuit board andelectrically interconnect the flip chip circuitry to the circuit boardconductor pattern.

[0030] Turning to FIG. 4 there is shown a cross-section of a CMOS imagesensor array 370 having a plurality of bumps or terminals 372 bonded toa surface 390 of the CMOS image sensor array 370. The bumps 372interconnect circuitry on the CMOS image sensor array 370 to signalprocessing circuits of an integrated circuit 374. In one embodiment, theintegrated circuit 374 includes circuitry employing CMOS technology.Incident light is received by the CMOS image sensor array 370 at asurface 380 thereof. In one embodiment, the CMOS image sensor arrayincludes the photo sensor diode 220 illustrated in FIG. 2, the locationof which is shown generally by reference character 382. The remainingFIG. 2 components (and other circuit elements as needed) are fabricatedinto the integrated circuit 374.

[0031] Optical filters can be placed adjacent the incident surface ofthe CMOS image sensor array 370 (that is, the surface 380) to filter outspecific wavelengths of light as determined by the characteristics ofthe filter. For example, a first plurality of photo sensors 220 in theCMOS image sensor array 370 can be made responsive to only red light byplacement of a filter blocking other spectral colors on the surface 380.In a similar manner, other photo sensors 220 can be made to respond onlyto blue or green light by appropriate spectral filtering. Signalsderived from the respective photo sensors representing the red, greenand blue light intensities can be combined within the circuitry of thesubstrate 374 for producing a color signal.

[0032] In one embodiment, the pitch of the pixels of the CMOS imagesensor array 370 is on the order of microns, and therefore toindividually access each image sensor, the pitch of the connections, ifconfigured to provide individual pixel access, must have the same pitch.In another embodiment of the present invention, adjacent or groupedpixels may be fabricated with different properties, for example eachpixel in a group of n pixels may have an optimal frequency response to aselected wavelength. In such an embodiment it may not be necessary toaccess individual pixels, but instead, the group of n pixels can beaccessed by a single interconnect bump. In yet another embodiment, theteachings of the present invention can be applied to a plurality ofimage sensors arranged in a line, rather than the two dimensional arrayillustrated in FIG. 1.

[0033] The array of bumps 372 can be formed using several differenttechniques, all presenting trade-offs between bump pitch, cost andfabrication simplicity. In one embodiment the bumps can be formed by asilk screening process or by the selective removal of a conductivematerial, typically using lithographic techniques. Familiar silkscreening processes can also be used to form the bump array.

[0034] The bumps can also be selectively formed by electroplating orelectrolessly over previously exposed metal or conductive regions in asemiconductor substrate. A mask, which is a transparent silica platebearing the bump pattern, is used to expose the regions where the bumpsare to be formed. The blank mask is coated with an ultraviolet lightabsorbing layer, such as iron oxide, making the entire mask opaque toultraviolet light. A thin layer of electron beam sensitive resistmaterial is placed on the plate and selective portions are exposed to anelectron beam; the exposed portions undergo a chemical change. Afterexposure, the exposed portions of the resist are removed by developingin a chemical solution. The iron oxide material is then selectivelyetched from the mask in those regions where the exposed resist has beenremoved

[0035] To prepare the integrated circuit, the surface 390 of the imagesensor 370 is covered with an ultraviolet light-sensitive organicmaterial, referred to as photoresist. The mask is then placed in contactwith the photoresist-covered wafer and the assembly is exposed toultraviolet light. The ultraviolet light shines through those portionsof the mask devoid of iron oxide and acidifies the exposed photoresist.The image sensor array 370 is developed in a basic solution ofsodium-hydroxide, causing the exposed photoresist to etch away. In thisway, the pattern on the mask has been transferred to the surface 390.The remaining photoresist is cured through a heat process.

[0036] The bumps 372 are then formed in the patterned surface 390 byelectroplating or electrodepositing a conductive material into theexposed areas. In the conventional electrodeposition technique, aquantity of metal (e.g., nickel) is accurately electrodeposited at themask opening points. If solder is used as the material for the bumps,the solder is placed in the openings and heated above its meltingtemperature to form solder bumps. The final shape of the bumps isdependent on the techniques used to form them and the material of whichthey are composed. Solder bumps are characteristically hemispherical.Bumps deposited by electroplating or electrolessly are likely to have arectangular cross section. After the bumps 372 are formed, the mask isremoved and a corrosion inhibitor applied to the entire surface 390,including the bumps 372. For example, solder bumps are coated with goldto inhibit corrosion.

[0037] The type of bumps formed on the surface 390 also determine thetechnique employed to attach the bumps 372 to the substrate 374. Whenthe bumps are formed of solder, a solder reflow attachment process isemployed to electrically interconnect and securely bond the individualsolder bumps 372 to the conductive pattern on the substrate 374. There-flow process involves first registering the solder bumps 372 withtheir respective mating conductive areas on the substrate 374 andre-heating or re-flowing the solder so as to metallurgically bond andthereby electrically interconnect the solder bumps 372 with thecorresponding conductors of the substrate 374. If the bump material isnickel, electrolessly or electrodeposited, a conductive adhesive,applied by a screen printing process, can be used to attach the twosurfaces. An anisotropic adhesive (i.e., conductive in substantially onedirection) can also be used. The adhesive is applied over the entiresurface, but conducts only in the regions where a crushing force hasbeen applied, as for instance, when the bump and its mating surface arebrought into physical contact.

[0038] It may be necessary to polish down and etch back the surface 380so that incident light can pass therethrough and reach the dopedsemiconductor regions forming the photo sensors 220. If the CMOS imagesensor array 370 is fabricated using a silicon substrate material, thenthe CMOS image sensor array 370 responds to those frequencies to whichsilicon is transparent, i.e., wavelengths in the infrared segment of thespectrum. As is known to those skilled in the art, the band gap of thesemiconductor material in which the photo sensors 220 are formeddetermines the wavelengths to which the semiconductor photo sensor 220responds, and thus the frequency sensitivity of the CMOS image sensorarray 370.

[0039] According to the teachings of the present invention, theinterconnect structure illustrated in FIG. 4 accommodates individualaccess and control over each pixel element or photo sensor 220. As aresult, optical special effects can be implemented in the photo sensorarray 370. Also, anomalies in the fabrication process may createvariations among the various photo sensors 220. In particular, slightvariations in doping level can affect the output photo sensor voltagefor identical incident light energy. After fabrication, the individualphoto sensors can be calibrated with known incident light and thereafterthe signal processing circuitry associated with each pixel can bedesigned to compensate for variations in output voltage for identicalinput incident light.

[0040]FIG. 5 illustrates three exemplary spaced-apart doped regionsrepresentative of the photo sensor 220. In particular, the pn junctionscomprise p-type substrate material 400 having spaced-apart n+ regions402 and n− regions 404 formed therein along a surface 403. Use of the n−region affords a larger depletion region for the collection of incidentphotons. The same structure can be fabricated with an n-type substrateand p-type doped regions formed therein.

[0041] In addition to the CMOS image sensors as discussed above, thephoto sensors of the present invention can also be implemented asSchottky-barrier diodes, metal-semiconductor-metal photodiodes, p-i-ndiodes, avalanche photodiodes, and heterojunction phototransistors.Also, field-effect and bipolar junction devices can also be employed asthe image sensors.

[0042] While the invention has been described with reference to apreferred embodiment, it will be understood by those skilled in the artthat various changes may be made and equivalent elements may besubstituted for the elements thereof without departing from the scope ofthe invention. The scope of the present invention further includes anycombination of the elements from the various embodiments set forthherein. In addition, modifications may be made to adapt a particularsituation to the teachings of the invention without departing from. Inparticular, the invention may be practiced in a variety of ways in avariety of circuit structures including structures formed with III-IVcompounds and other semiconductor materials. Therefore, it is intendedthat the invention not be limited to the particular embodimentsdisclosed, but that the invention will include all other constructions,not expressly identified herein, which fall within the scope of theappended claims.

What is claimed is:
 1. An integrated circuit device comprising: a firstintegrated circuit comprising a plurality of discretely operableelectrical elements and a plurality of conductive interconnect elementsin electrical communication with one or more of said plurality ofdiscretely operable electrical elements; and a second integrated circuitcomprising operative circuitry and a plurality of connection pads formedon a surface thereof and in electrical communication with said pluralityof conductive interconnect elements.
 2. The integrated circuit device ofclaim 1 wherein the number of discretely operable electrical elements isequal to the number of interconnect elements.
 3. The integrated circuitdevice of claim 1 wherein the pitch of the plurality of interconnectelements is equal to the pitch of the plurality of connection pads. 4.The integrated circuit device of claim 1 wherein the operative circuitryof the second integrated circuit operates in conjunction with theplurality of electrical elements of the first integrated circuit.
 5. Theintegrated circuit device of claim 1 wherein the plurality ofinterconnect elements is equal to the plurality of discretely operableelectrical elements.
 6. The integrated circuit device of claim 1 whereinthe plurality of interconnect elements comprise a plurality ofconductive bumps.
 7. The integrated circuit device of claim 6 whereinthe plurality of conductive bumps are formed by forming a conductivelayer over the plurality of electrical elements and selectively removingregions of the conductive layer such that the remaining regions form theconductive bumps.
 8. The integrated circuit of claim 7 wherein theselective removal of regions of the conductive layer is controlled by alithographic process using a mask to identify the regions to be removed.9. The integrated circuit of claim 1 wherein each one of the pluralityof discretely operable electrical elements comprises operative circuitryand a conductive pad in electrical communication with said operativecircuitry, and wherein each one of said plurality of conductive pads isfurther in electrical communication with one of the plurality ofinterconnect elements, and wherein each one of said plurality ofconductive pads is exposed through a lithographic process operative onthe surface of the first integrated circuit to provide for the formationof the plurality of interconnect elements in electrical communicationtherewith.
 10. The integrated circuit of claim 1 wherein each one of theplurality of conductive interconnect elements is affixed to one of theplurality of connection pads by the use of a conductive adhesive. 11.The integrated circuit device of claim 1 wherein the plurality ofelectrical elements are arranged in an array.
 12. The integrated circuitdevice of claim 1 wherein the plurality of electrical elements arearranged in a linear pattern.
 13. The integrated circuit device of claim1 wherein the area devoted to the plurality of electrical elements onthe first integrated circuit is maximized.
 14. An integrated circuitdevice comprising: a first integrated circuit including a plurality ofdiscretely operable photo sensors, wherein an operational parameter ofeach of the plurality of photo sensors is related to the light incidenton said first integrated circuit, and wherein said first integratedcircuit further comprises a plurality of conductive interconnectelements each one in electrical communication with one or more of saidplurality of photo sensors; and a second integrated circuit having aplurality of connection pads formed on a surface thereof and inelectrical communication with said plurality of conductive interconnectelements.
 15. The integrated circuit device of claim 14 wherein thesecond integrated circuit comprises operative circuitry for determiningthe operational parameter of a photo sensor related to the incidentlight.
 16. The integrated circuit device of claim 14 wherein the surfaceof the first integrated circuit exposed to the incident light isprocessed so as to maximize the light received by the plurality of photosensors.
 17. The integrated circuit device of claim 14 wherein the firstintegrated circuit comprises a semiconductor substrate of a firstconductivity type and a plurality of spaced apart doped semiconductorregions of a second conductivity type formed in a surface of thesemiconductor substrate, and wherein a reverse bias potential is appliedto the semiconductor substrate and the doped regions so as to create adepletion region therebetween.
 18. The integrated circuit device ofclaim 14 wherein the first integrated circuit comprises an image sensorarray, and wherein the fill factor of the image sensor array ismaximized.
 17. The integrated circuit device of claim 14 wherein theplurality of conductive interconnect elements is equal in number to theplurality of photo sensors.
 18. The integrated circuit device of claim14 wherein each one of the plurality of conductive interconnect elementscomprises a conductive surface extending above a surface of the firstintegrated circuit.
 19. The integrated circuit device of claim 18wherein the conducting surface extending above the surface of the firstintegrated circuit comprises a conductive bump.
 20. The integratedcircuit of claim 19 wherein the conductive bumps are formed by forming aconductive layer over the plurality of electrical elements andselectively removing regions of the conductive layer such that theremaining regions form the conductive bumps.
 21. The integrated circuitof claim 20 wherein the selective removal of regions of the conductivelayer is controlled by a lithographic process using a mask to identifythe regions to be removed.
 22. The integrated circuit of claim 14wherein each one of the plurality of discretely operable photo sensorscomprises operative circuitry and a conductive pad in electricalcommunication with said operative circuitry, and wherein each one ofsaid plurality of conductive pads is further in electrical communicationwith one of the plurality of interconnect elements, and wherein each oneof said plurality of conductive pads is exposed through a lithographicprocess operative on the surface of the first integrated circuit toprovide for the formation of the plurality of interconnect elements inelectrical communication therewith.
 23. The integrated circuit of claim14 wherein each one of the plurality of conductive interconnect elementsis affixed to one of the plurality of connection pads using a conductiveadhesive.
 24. The integrated circuit device of claim 14 wherein theplurality of photo sensors are arranged in an array.
 25. The integratedcircuit device of claim 14 wherein the plurality of photo sensors arearranged in a linear pattern.
 26. A method for fabricating an integratedcircuit device comprising: fabricating a first integrated circuitincluding a plurality of discretely operable electrical elements;fabricating a plurality of conductive interconnect elements inelectrical communication with one or more of said plurality ofdiscretely operable electrical elements; fabricating a second integratedcircuit having a plurality of connection pads formed on a surfacethereof; and positioning each one of the plurality of conductiveinterconnect elements in electrical communication with one of theplurality of connection pads.
 27. The method of claim 26 wherein thestep of fabricating the plurality of conductive interconnect elementscomprises forming a conductive layer over the plurality of electricalelements and selectively removing regions of the conductive layer suchthat the remaining regions form the conductive interconnect elements.28. The method of claim 27 wherein the step of selectively removingfurther comprises applying a lithographic mask to the surface of theconductive layer and removing regions of the conductive layer ascontrolled by the lithographic mask.
 29. The method of claim 26 whereineach one of the plurality of electrical elements comprises operativecircuitry and a conductive pad in electrical communication with saidoperative circuitry, and wherein each one of said plurality ofconductive pads is further in electrical communication with one of theplurality of interconnect elements, and wherein the method furthercomprises exposing each one of said plurality of conductive pads using alithographic mask applied to the operative surface of the firstintegrated circuit and forming the plurality of interconnect elements inelectrical communication therewith through the mask.
 30. The method ofclaim 26 wherein the step of positioning further comprises affixing eachone of the plurality of conductive interconnect elements to one of theplurality of connection pads using a conductive adhesive.
 31. The methodof claim 26 wherein one of each of the plurality of discretely operableelectrical elements comprises a photo sensor.
 32. The method of claim 26wherein the plurality of photo sensors are fabricated by the step ofdoping a substrate of a first conductivity type with a dopant of asecond conductivity type.